The present invention relates to a microprocessor, and more particularly to instruction encoding and an internal control logic structure suitable for reducing the size and improving the performance of an LSI microprocessor.
In a conventional 8-bit microprocessor instruction code, an instruction set primarily for use in an accumulator operation is based on a one-byte instruction. An example of such an instruction set is that used in an 8-bit microprocessor HD 6303X (Hitachi). In a 16-bit microprocessor, general purpose register and an operand address (effective address EA) operation mode have been introduced. As a result, code length for one instruction is more than one byte. An example of such an instruction set is one used in the 16-bit microprocessor 8086 (Intel).
In order to efficiently execute compiling in a high level language, an operation executed by one instruction and generation of an operand address may be independently designated. Namely, as a function of one instruction, the designation of operation and the designation of operand addressing mode are independently effected. This is called orthogonalization of the operation and the operand addressing, and an instruction having such a function is called an orthogonal instruction. An example of such an instruction is one used in the 16-bit microprocessor HD 68000 (Hitachi). Thus, by independently designating the operation and the operand addressing mode, the operand addressing mode can be set for each operation. In this method, however, the code length of one instruction is long. For example, in the instruction set for HD 68000, a minimum instruction code length is of 2-byte length and the instruction code length is thus expanded by a byte unit.
A microprocessor structuring method of a microprogramming system of JP-A-56-108149 discloses a microprocessor structuring method for an instruction which puts a weight on the orthogonality of the operation and the operand addressing mode. In the disclosed structuring method, an entire code which designates the operand and the operand addressing mode is decoded to generate start addresses of a plurality of microprograms such as operation execution microprogram and operand addressing microprogram. In order to execute one instruction, subroutines of the microprograms are sequentially started by those start addresses. Since the operation and the operand addressing mode are independently designated in one instruction, the subroutine method is effective in reducing the volume of the microprograms.
In the above prior art methods, the minimum code length of the instruction is long and no attention is paid to the logical scale of the instruction decoder for decoding the entire long instruction code. As a result, the code efficiency (a reciprocal of the total instruction code length actually used) of the dynamic instruction code in the execution of the program is lowered and the scale of the instruction decoder expands.